Title:
演算装置、電子制御装置及び演算方法
Document Type and Number:
Japanese Patent JP6648663
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To minimize delay of timing at which barrier synchronization is completed, in an arithmetic unit which executes parallel processing using barrier synchronization by a plurality of processors.SOLUTION: An arithmetic unit 2 having a plurality of processors 31-3n and executing parallel processing using barrier synchronization by the plurality of processors sets the processor among the plurality of processors 31-3n that is in a synchronization waiting state as an interrupt request destination.SELECTED DRAWING: Figure 1
Inventors:
Takato Kusumoto
Application Number:
JP2016188164A
Publication Date:
February 14, 2020
Filing Date:
September 27, 2016
Export Citation:
Assignee:
株式会社デンソー
International Classes:
G06F9/48; G06F9/52
Domestic Patent References:
| JP52149931A |
Foreign References:
| US20160110195 |
Attorney, Agent or Firm:
Patent Business Corporation Sato International Patent Office