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Title:
半導体プロセス制御のためのパターン付ウェハ形状測定
Document Type and Number:
Japanese Patent JP6650889
Kind Code:
B2
Abstract:
Wafer geometry measurement tools and methods for providing improved wafer geometry measurements are disclosed. Wafer front side, backside and flatness measurements are taken into consideration for semiconductor process control. The measurement tools and methods in accordance with embodiments of the present disclosure are suitable for handling any types of wafers, including patterned wafers, without the shortcomings of conventional metrology systems.

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Inventors:
Bucadala Pradeep
Sinha Jay Deep
Application Number:
JP2016575021A
Publication Date:
February 19, 2020
Filing Date:
April 23, 2015
Export Citation:
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Assignee:
KLA Corporation
International Classes:
H01L21/304; B24B37/005; G01B21/30; G03F7/20; H01L21/66
Domestic Patent References:
JP2013527972A
JP2010529659A
JP2011249627A
JP2002018701A
JP2004247476A
JP2005197578A
JP2006300676A
JP2000094301A
JP2004029735A
Attorney, Agent or Firm:
Patent Corporation yki International Patent Office



 
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