Title:
半導体設計支援装置、半導体設計支援方法、及び半導体設計支援プログラム
Document Type and Number:
Japanese Patent JP6672791
Kind Code:
B2
Abstract:
A memory stores layout data of a semiconductor circuit. A processor searches for a plurality of wiring routes on the basis of a plurality of cost calculating formulas that respectively represent a plurality of design rules, and on the basis of the layout data, wherein the plurality of wiring routes are a plurality of candidates for a wiring route that corresponds to a processing target net that is connection information that needs to be changed in the semiconductor circuit, and respectively satisfy the plurality of design rules. Then, the processor generates display information that displays the plurality of wiring routes obtained by the search.
Inventors:
Mitsuyoshi Fujiwara
Application Number:
JP2015256638A
Publication Date:
March 25, 2020
Filing Date:
December 28, 2015
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F30/39; G06F30/394; H01L21/82
Domestic Patent References:
| JP8022481A | ||||
| JP2006172143A | ||||
| JP6052261A |
Foreign References:
| US20150242559 | ||||
| US20080163150 | ||||
| CN103380427A |
Attorney, Agent or Firm:
Yoshiyuki Osuga
Hiroyoshi Aoki
Amada Masayuki
Hiroyoshi Aoki
Amada Masayuki