Title:
画像プロセッサ用多機能実行レーン
Document Type and Number:
Japanese Patent JP6789287
Kind Code:
B2
Abstract:
An apparatus is described that includes an execution unit having a multiply add computation unit, a first ALU logic unit and a second ALU logic unit. The ALU unit is to perform first, second, third and fourth instructions. The first instruction is a multiply add instruction. The second instruction is to perform parallel ALU operations with the first and second ALU logic units operating simultaneously to produce different respective output resultants of the second instruction. The third instruction is to perform sequential ALU operations with one of the ALU logic units operating from an output of the other of the ALU logic units to determine an output resultant of the third instruction. The fourth instruction is to perform an iterative divide operation in which the first ALU logic unit and the second ALU logic unit operate during to determine first and second division resultant digit values.
Inventors:
Artem Vasiliev
Jason Rupert Redgrave
Albert Makesner
Ofer Shacham
Jason Rupert Redgrave
Albert Makesner
Ofer Shacham
Application Number:
JP2018519299A
Publication Date:
November 25, 2020
Filing Date:
October 19, 2016
Export Citation:
Assignee:
Google LLC
International Classes:
G06F9/38; G06F7/535; G06F15/80; G06F17/10; G06T1/20
Domestic Patent References:
| JP7234778A | ||||
| JP2000222208A | ||||
| JP57162030A |
Foreign References:
| US20050219422 |
Other References:
尾形幸亮,外4名,ALU Cascadingのための動的命令スケジューラ,先進的計算基盤システムシンポジウムSACSIS2008論文集,日本,社団法人情報処理学会,2008年 6月 4日,pp.105~114
恒川佳隆,外2名,高基数に基づく選択型高速除算器の構成,電気学会論文誌C,日本,社団法人電気学会,1998年 6月 1日,Vol.118-C,No.6,pp.833~841
恒川佳隆,外2名,高基数に基づく選択型高速除算器の構成,電気学会論文誌C,日本,社団法人電気学会,1998年 6月 1日,Vol.118-C,No.6,pp.833~841
Attorney, Agent or Firm:
Fukami patent office