Title:
容量検出回路、入力装置
Document Type and Number:
Japanese Patent JP7432419
Kind Code:
B2
Abstract:
The present disclosure provides a capacitance detection circuit capable of reducing a chip area. The present disclosure relates to a capacitance detection circuit and an input device. A sense pin of the capacitance detection circuit is connected to a sensor electrode. A first driving unit applies a high voltage or a low voltage to the sense pin. A second driving unit applies the high voltage or the low voltage to a first terminal of a reference capacitor. A third driving unit applies the high voltage or the low voltage to a second terminal of the reference capacitor. A first switch is disposed between the sense pin and the first terminal of the reference capacitor. A second switch is disposed between an input of a post-stage circuit block and the first terminal of the reference capacitor.
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Inventors:
Yuji Shimada
Application Number:
JP2020057686A
Publication Date:
February 16, 2024
Filing Date:
March 27, 2020
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
G06F3/041; G01R27/26; G06F3/02; G06F3/044
Domestic Patent References:
| JP2019211898A | ||||
| JP2015156159A | ||||
| JP2014045475A | ||||
| JP2006184273A | ||||
| JP2012164082A | ||||
| JP8272529A | ||||
| JP2008542760A | ||||
| JP2021157546A |
Foreign References:
| US20100245286 | ||||
| US20210034178 | ||||
| US20100042346 | ||||
| KR101317227B1 | ||||
| CN103324366A | ||||
| US20190302928 | ||||
| US20180209858 |
Attorney, Agent or Firm:
Kenki Morishita
Taiki Maya
Taiki Maya