Document Type and Number:
Japanese Patent JPH0432572
Kind Code:
B2
Abstract:
PURPOSE:To simplify constitution and to reduce chip size, by providing complementary constitution for only one input and using the constitution of an MOSFET and a load element for other inputs. CONSTITUTION:When all inputs a0-a3 are at a level H, all N channel MOSFETs Q1-Q4 turn on and an NAND gate A geneates an output oul with a level L. The resistance of the load resistance RL1, however, is made much greater than an on-resistance. When at least one of the inputs a0-a3 is at the level L, at least one of the N channel FETs Q1-Q4 turns off to obtain infinite serial resistance and the output oul goes up to the level H. Two FETs Q1 and Q2 are in complementary constitution. An NOR gate B also includes two FETs in complementary constitution. Further, active elements are usable as load elements RL1 and RL2. Therefore, the constituion is simplified and the size is reduced.
Application Number:
JP7953782A
Publication Date:
May 29, 1992
Filing Date:
May 11, 1982
Export Citation:
International Classes:
H03K17/687; H03K19/0948; H03K23/60