Japanese Patent JPH0439690

B2

A programmable high resolution timing system includes a selectable modulus prescaler counter (16). In one embodiment a high frequency clock (14) is coupled to a prescaler counter (16) which provides an output signal (T_A/T_M) every predetermined number of clock pulses. The prescaler (16) is coupled to a period counter (18) which provides a period signal (To) after a predetermined number of prescaler output signal pulses. The prescaler (16) and period counter (18) are coupled to a memory (32) which stores data corresponding to the selected modulus of the prescaler (16) and the number of counts by which the period counter (18) output signal is to be delayed. The period resolution is thus made substantially equal to the resolution of the high frequency clock (14) by varying the prescaler (16) modulus at programmable intervals.

JP4046528	Electronic circuits and semiconductor devices
JPH0587619	[Name of invention] Clock signal generation circuit

JP5931084A

June 30, 1992

March 27, 1984

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G06F1/06; G06F1/04; H03K5/15; H03K23/66

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