Document Type and Number:
Japanese Patent JPH0440894
Kind Code:
B2
Abstract:
A logic circuit (20) is provided for receiving an input signal and for generating a delayed output signal being clocked by first and second non-overlapping clock phases. Logic circuit (20) includes a voltage supply (V). A precharge transistor (30) is interconnected to the voltage supply (V) and is clocked by the first clock phase. A discharge transistor (32) is interconnected to the precharge transistor (30) thereby defining a first node (A) and is clocked by the second clock phase to conditionally discharge the first node (A). An input logic circuit (34) is interconnected to the discharge transistor (32) thereby defining a second node (B) for providing a discharge path from the first node (A) to a ground voltage potential, the input logic circuit (34) is connected to receive the input signal. An output transistor (36) is interconnected to the first node (A) for generating the delayed output signal. The output transistor (36) is clocked by the second clock phase. A capacitor (38) is interconnected to the first node (A) and the output transistor (36) and is clocked by the second clock phase for maintaining the first node (A) at a predetermined voltage level by a bootstrapping operation.
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Inventors:
YANGU IAN EI
JIANSUN CHAARUZU BII
HIRUDOBURANDO DEIUIDO BII
JIANSUN CHAARUZU BII
HIRUDOBURANDO DEIUIDO BII
Application Number:
JP50146380A
Publication Date:
July 06, 1992
Filing Date:
May 05, 1980
Export Citation:
Assignee:
MOSTEK CORP
International Classes:
H03K5/05; H03K3/356; H03K5/08; H03K19/017; H03K19/0185; H03K19/096; H03K19/20; H03K23/00; H03K23/42; H03K23/44