Title:
【発明の名称】集積回路のリバースエンジニアリングを防止するための構造
Document Type and Number:
Japanese Patent JPH09502834
Kind Code:
A
Abstract:
Embodiments according to the present invention provide tamper resistant structures which make it more difficult to reverse engineer integrated circuits. In one embodiment, a tamper resistant structure on a passivation layer leaves portions of the passivation layer exposed. Mechanical or chemical removal of the tamper resistant structure damages exposed portions of the passivation layer and makes reverse engineering difficult. Other embodiments of the tamper resistant structure include patterned and unpatterned structures containing hard materials, chemically resistant materials, amalgams, fibrous materials, and/or meshes attached to a passivation layer. Tamper resistant structures can also be provided between layers of the active circuitry.
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Inventors:
Daum, keith, edwin
Application Number:
JP50515295A
Publication Date:
March 18, 1997
Filing Date:
June 24, 1994
Export Citation:
Assignee:
NATIONAL SEMICONDUCTOR CORPORATION
International Classes:
H01L21/314; H01L21/82; H01L23/58; H01L27/02; H01L27/118; (IPC1-7): H01L21/314; H01L27/118
Attorney, Agent or Firm:
Kaoru Furuya (2 outside)