PURPOSE: To generate an accurate clock pulse with simple constitution, by controlling the oscillating frequency of a VCO with a control signal which is delivered from a latch circuit.

CONSTITUTION: A kind of PLL circuit is formed with a VCO1, a frequency divider 2, a differentiating circuit 3, a latch circuit 4, etc. The level "1" or "0" of a clock pulse (d) obtained at a time point when a differentiating pulse (b) is delivered is held until the next pulse (b) arrives, i.e., until the region "1" or "0" of a PCM signal (a) is varied. With this held level the oscillating frequency (b) of a VCO1 that is a factor by which the frequency of the pulse (d) is controlled. In this case, the frequency of the pulse (d) is high, and the pulse (d) has a phase advanced by θ1 compared with a differentiating pulse (b2) and is set at level "0" at a time point when the pulse (b2) is delivered. Thus the circuit 4 holds the level "0" to lower the oscillating frequency (c) of the VCO1. As a result, the frequency itself of the pulse (d) is lowered.