Title:
3次元デバイスの製造方法
Document Type and Number:
Japanese Patent JP4085459
Kind Code:
B2
Abstract:
A three-dimensional device contains two layers, each having a memory cell array, an input/output control circuit for routing signals into and out of the array, and row and column decoders for controlling the array. The input/output control circuit, row decoder and column decoder of one layer overlap the corresponding items of the other layer.
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Inventors:
Tatsuya Shimoda
Satoshi Inoue
Satoshi Inoue
Application Number:
JP4988398A
Publication Date:
May 14, 2008
Filing Date:
March 02, 1998
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H01L27/00; G11B5/84; G11C11/401; H01L21/336; H01L21/68; H01L21/762; H01L21/77; H01L21/822; H01L21/8242; H01L21/8244; H01L21/8246; H01L21/84; H01L21/98; H01L23/48; H01L25/065; H01L27/06; H01L27/10; H01L27/105; H01L27/108; H01L27/11; H01L27/12; H01L29/786; H01L39/02; H01L39/24; H01L43/12; H01L31/101
Domestic Patent References:
| JP8213548A | ||||
| JP8204123A | ||||
| JP1140753A | ||||
| JP9148207A | ||||
| JP5160340A | ||||
| JP7506936A | ||||
| JP7029783A | ||||
| JP6268154A |
Attorney, Agent or Firm:
Masahiko Ueyanagi
Osamu Suzawa
Osamu Suzawa