PURPOSE: To provide a 5-division circuit which has a duty ratio of 50%, can facilitate the correction of delay, and can freely set a sequence of combinations with other circuits.

CONSTITUTION: The clock pulses inputted from a CLK are inputted to two AND gates 2 and 6, four D type flip-flops 3, 4, 5 and 7, and an OR gate 8 respectively via a buffer 1 consisting of a NOT gate. Then the 1:1 relation is secured between H and L levels of output QE of the gate 8 which has the inputs from the flip-flop circuits 4 and 7.