Title:
ABNORMAL OPERATION DETECTING METHOD FOR FACILITY
Document Type and Number:
Japanese Patent JP3217647
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To surely detect an abnormal operation while allowing lag in timing at the change point of a binary signal caused by facility.
SOLUTION: An abnormal facility operation detector 2 is provided with a communication means 3 for monitoring the state, etc., of the contact of a programmable controller(PC) 1. Besides, a reference operation pattern storage means 5 previously stores a reference operation pattern for detecting the abnormal operation, a comparing means 7 compares the on/off timing of the contact of the PC 1 in the real operation of the facility with the timing of the reference operation pattern and when the both are not matched with each other, it is judged that an abnormal operation is generated at the facility. In this case, allowable time width for allowing lag in timing caused by the facility is set to the reference operation pattern. Therefore, the lag in timing generated at the normally operating facility is not erroneously detected as the abnormal operation but the abnormal operation can be surely detected.
Inventors:
Hajime Naohara
Atsushi Tsuji
Futoshi Fuchida
Atsushi Tsuji
Futoshi Fuchida
Application Number:
JP17260295A
Publication Date:
October 09, 2001
Filing Date:
July 07, 1995
Export Citation:
Assignee:
MATSUSHITA ELECTRIC WORKS,LTD.
International Classes:
G05B1/01; G05B19/048; G05B19/05; G05B23/02; (IPC1-7): G05B19/048; G05B1/01; G05B23/02
Domestic Patent References:
| JP5189026A | ||||
| JP511835A | ||||
| JP2198817A | ||||
| JP63233407A |
Attorney, Agent or Firm:
Keisei Nishikawa (1 person outside)