PURPOSE: To easily remove a semiconductor integrated circuit generating the deterioration of a transistor, by fixing the binary signals respectively applied to the FFs of an internal circuit to the value of one of two values.

CONSTITUTION: A plurality of FFs for amplifying the difference potential of bit wires 7 respectively forming pairs are contained in a sense amplifying circuit 5 and FFs for latching input and output data are contained in an input/output circuit 6. High power supply voltage is applied to each of the internal circuits of the dynamic memory containing the circuits 5, 6 and the signal fixed to one of binary signals of a high level VH and low level VL, for example, to the level VL is applied as input data DT1 to perform a sequential writing operation test to the addresses of a memory array 44 determined by an address signal AD according to line and row address control signals RAS, CAS. Herein, since the data DT1 is fixed to the level VL, each of the transistor pairs of the FFs contained in the circuits 5, 6 always becomes an ON/OFF state. Therefore, the transistor on the side repeating an ON state is accelerated in the deterioration of a characteristic and, when deterioration is generated, the FFs become ill-balanced.