Title:
ACCESS CONTROL SYSTEM FOR SHARE MEMORY
Document Type and Number:
Japanese Patent JPS61114362
Kind Code:
A
Abstract:
PURPOSE:To realize apparent simultaneous access and to reduce hardware by applying the phase division to the timing with which two processors give access to a share memory at a speed higher enough than the access time of those processors to the share memory. CONSTITUTION:A selector DS selects the data buses of microprocessors A and B with a selection clock. An access timing control circuit ATC of a share memory produces the write signal as well as enable signals of gates GA and GB by the signals of both processors A and B as well as the selection clock. The phase division is applied to the timing with which both processors a and B give access to the share memory at a speed higher enough than the access time of both processors A and B to the share memory.
Inventors:
TAKAI TOKIO
Application Number:
JP23501084A
Publication Date:
June 02, 1986
Filing Date:
November 09, 1984
Export Citation:
Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
G06F15/16; G06F9/34; G06F9/38; G06F12/00; G06F13/16; G06F15/177; (IPC1-7): G06F13/18; G06F15/16
Attorney, Agent or Firm:
Keiichi Yamamoto