To reduce resistance of a gate line and to suppress reduction of a numerical aperture of a pixel as far as possible.
In an active matrix substrate 20a provided with a plurality of pixels provided in a matrix shape, a plurality of source lines 4 extended in parallel with each other between respective pixels, a plurality of gate lines 2 extended in parallel with each other between respective pixels in a direction crossing the source lines 4 and having annular parts K opened in positions superposed on respective source lines 4 respectively and thin film transistors disposed for each pixel and each having a semiconductor layer 1 wherein a plurality of channel regions C1, C2 and C3 are formed correspondingly to the annular part K of the gate line 2, the channel regions C2 and C3 of the semiconductor layer 1 are provided so as to be superposed on the respective source lines 4.
COPYRIGHT: (C)2007,JPO&INPIT
YOSHIDA KEISUKE
NAKAJIMA MUTSUMI
Yuji Takeuchi
Kazutoshi Nakayama