ADD DROP MULTIPLEXER DEVICE

Japanese Patent JP3409234

B2

PROBLEM TO BE SOLVED: To suppress the increase of a hardware scale with the acceleration of transmission speed and to shorten a fault recovering time by generating a transmission path clock signal and a transmission frame phase signal from an inter-station signal.
SOLUTION: In a normal operation, an add drop part 12 and an inter-station signal transmitting part 14 are synchronized with a clock which is extracted from the inter-station signal received from a W side transmission path so as to execute an operation. Therefore, when a certain fault occurs in the W side transmission path and an inter-station signal receiving part 10 becomes a state with signal disconnection and clock signal disconnection, etc., the inter-station signal receiving part 10 generates a transmission frame signal and the transmission path clock signal which are synchronized with the clock extracted from the inter-station signal and with the frame phase of the inter-station signal in order to prevent an E side transmission path from being affected, incorporates an oscillation circuit for generating a free-running transmission path frame signal which is synchronized with a free-running clock signal and the free- running transmission path clock signal.

JP5234816	Communication control method and communication control system
WO2002067549	FAILURE REDUNDANCY BETWEEN MODEM INTERFACE CARDS AND OUTDOOR UNITS IN A WIRELESS COMMUNICATION SYSTEM

Yoshihiko Uematsu
Shinji Matsuoka
Masato Tomizawa

JP23367896A

May 26, 2003

August 16, 1996

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Nippon Telegraph and Telephone Corporation

H04B1/74; H04B1/76; H04J3/00; H04J3/08; H04L12/42; H04L29/08; (IPC1-7): H04J3/08; H04B1/74; H04B1/76; H04J3/00; H04L12/42; H04L29/08

JP677977A
JP5227177A
JP5227116A
JP8237215A

Keiichi Yamamoto

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