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Patent Searching and Data


Title:
ADDRESS DETECTION SYSTEM
Document Type and Number:
Japanese Patent JPS5785145
Kind Code:
A
Abstract:

PURPOSE: Not to requre the same number of registers as the number of break point addresses, by using a break point address detection memory so that the break point address is set to said memory.

CONSTITUTION: A break point (BP) address to be set is stored in a memory 22. Subsequently, one BP address is read out from the memory 22. A flag 1 is written in an address of a BP address detection memory 14 indicated by lower M bits of the read-out address. Subsequently, a program of a microprocessor unit (MPU) 10 is executed. When the memory 14 is accessed and the BP address is set, an output of the memory 14 becomes "1", and the program of the MPU10 is stopped. On the other hand, a controlling circuit 18 is operated, upper L bits of a program address in that case are inputted, also lower M bits are inputted, they are made a BP address of N=M+L, and whether it is present in the memory 22 or not is checked. As a result of said check, if it is present, processing required for debug is executed.


Inventors:
KIMURA MASAHARU
Application Number:
JP16221180A
Publication Date:
May 27, 1982
Filing Date:
November 18, 1980
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F9/32; G06F11/28; G06F11/36; (IPC1-7): G06F9/06; G06F9/32; G06F11/00
Domestic Patent References:
JPS54112138A1979-09-01