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Title:
AMPLITUDE LIMITER CIRCUIT
Document Type and Number:
Japanese Patent JPH03286617
Kind Code:
A
Abstract:

PURPOSE: To output a signal with an amplitude smaller than that of a power supply by connecting plural NMOS transistors(TRs) in diode connection in series and giving an input signal to one gate and outputting an output signal from a drain.

CONSTITUTION: When a level of an input terminal 16 is 0V, no current flows to an amplitude limiter circuit, and the voltage at an output terminal 15 gets lower than the voltage of a power supply 12 by a sum of threshold levels of TRs 11, 13. This state continues till a voltage applied to the input terminal 16 increases from 0V and reaches a sum of threshold levels of TRs 14, 17. When an applied voltage to the input terminal 16 is larger than 2VT (VT is a threshold level of each TR), the TRs 14, 17 are turned on and a level of the output terminal 15 starts decreasing. Moreover, when a level at the input terminal 16 rises, the TR 14 reaches the non-saturation region and an output voltage is not much reduced.


Inventors:
HAYAKAWA HISATO
Application Number:
JP8794390A
Publication Date:
December 17, 1991
Filing Date:
April 02, 1990
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03K5/08; H03K19/0185; (IPC1-7): H03K5/08; H03K19/0185
Attorney, Agent or Firm:
Shigetaka Awano (1 person outside)