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Title:
ANALOG-DIGITAL CONVERTER
Document Type and Number:
Japanese Patent JPS62203424
Kind Code:
A
Abstract:

PURPOSE: To use a comparator operationable at nearly a speed of an input signal by using a synchronizing signal period as a charging mode of a comparator and using other period as a comparison mode so as to eliminate the need for the mode changeover.

CONSTITUTION: A synchronizing recovery circuit 10 generates a rectangular wave signal synchronously with an inputted video signal. A signal of nearly 14.3MHz is supplied to each of latches 51∼5n as a clock pulse and a synchronizing signal is fed to each of comparators 41∼4n as a clock. Thus, the mode is continuously the charging mode during the synchronizing period and a prescribed electric charge is held in a summing capacitor 45. In periods other than the synchronizing period, the mode is always the comparison mode and a voltage charged in the summing capacitor 45 at the charging mode and the input VX are added and the result is compared with a voltage VT of an inverter 43. The voltage depending on the polarity is outputted from the inverter 43 and sampled at a high speed by the latches 51∼5n.


Inventors:
OGAWARA TAKESHI
Application Number:
JP4695386A
Publication Date:
September 08, 1987
Filing Date:
March 04, 1986
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03M1/12; H03M1/36; (IPC1-7): H03M1/12; H03M1/36
Attorney, Agent or Firm:
Tadao Hirata



 
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