PURPOSE: To suppress the rise of the ON resistance of an analog switching MOS transistor without increasing the size of the transistor, by connecting a boosting capacitance between the output terminal of a delay circuit and the gate of the analog switching MOS transistor.

CONSTITUTION: When a IN signal is changed from a low level to a high level, an N-channel transistor 2 goes to an OFF state. At this time, a load capacitance CL and the boosting capacitance CB are charged until a voltage between both ends of respective capacitance goes to a voltage VDD. When an output being delayed by the delay time (td) of the delay circuit 3 is changed to the high level, a P-channel transistor 1 goes to the OFF state. At this time, since one end on the delay circuit side of the boosting capacitance CB goes to a power source potential VDD, a OUT1 output node is boosted. A driving circuit 10 outputs a OUT1 signal boosted by 0.6V higher than the power source voltage VfDD only in the high level period of the control clock IN. In such way, it is possible to reduce the ON resistance at the time of ON-driving the N-channel transistors TN of analog switches S....