Title:
ANALYSIS PREVENTION METHOD OF COMBINATIONAL CIRCUIT AND SYSTEM
Document Type and Number:
Japanese Patent JPH08102656
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To block analysis of a combinational circuit by changing the design of a combinational circuit while maintaining a circuit function. SOLUTION: This method starts by selecting more than one connection that constitutes thin set. Once the thin set is selected, a sub circuit which includes at least all of elements that are sources or destinations of selected connections in the thin set is replaced with a replacing circuit that has the same function. In this way, it is possible to block reverse engineering of an original circuit by changing an element.
Inventors:
FURANSHISUKO KOREERA
Application Number:
JP21475995A
Publication Date:
April 16, 1996
Filing Date:
August 23, 1995
Export Citation:
Assignee:
IBM
International Classes:
H03K19/177; (IPC1-7): H03K19/177
Attorney, Agent or Firm:
Kiyoshi Goda (2 outside)