To provide an apparatus and a method capable of efficient data transfer within a system.

A first bus 112A is operatively coupled to the plurality of processors 102A-102D of a multiprocessor system such that data may be transferred to and from the processors at a first frequency F1. A second bus 112B is operatively coupled to a memory interface circuit 104, a PCI (peripheral component interconnect) circuit 108, and an external interface circuit 110 such that data may be transferred to and from the interface circuits at a second frequency F2. An asynchronous boundary circuit 120 transfers data between the first and second busses 112A, 112B at the respective first and second frequencies F1, F2.