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Patent Searching and Data


Title:
ARRANGING AND WIRING APPARATUS AND LAYOUT METHOD FOR LSI
Document Type and Number:
Japanese Patent JP2001291776
Kind Code:
A
Abstract:

To realize layout capable of preventing malfunction due to inter-wiring crosstalk without using any shield electrode for increasing a parasitic capacity.

After blocks and micros are arranged, objective wiring for preventing cross-talk is arranged in the m-th wiring layer, and a wiring grid with (n) pieces each from the most adjacent wiring at the both sides of the objective wiring to the outside in parallel in the same layer and a wiring grid positioned just above the objective wiring belonging to the (m+k)th wiring layer (k is more than 0 and not more than n) in the upper layer than that of the objective wiring and a wiring grid with (n-k) pieces each from the most adjacent wiring at the both sides of the wiring grid to the outside are formed as a wiring inhibition area, and all the signal wiring other than the objective wring is set while the wiring inhibition area is by-passes.


Inventors:
HIKIBA RUMI
Application Number:
JP2000106090A
Publication Date:
October 19, 2001
Filing Date:
April 07, 2000
Export Citation:
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Assignee:
NEC MICROSYSTEMS LTD
International Classes:
G06F17/50; H01L21/82; H01L21/822; H01L27/04; (IPC1-7): H01L21/82; G06F17/50; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)