Title:
ASYNCHRONOUS ARITHMETIC UNIT
Document Type and Number:
Japanese Patent JP3544841
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To unnecessitate the initializing operation of an arithmetic unit in continuous calculation and to improve arithmetic efficiency by interrupting an arithmetic loop after detecting the last loop of calculation and permitting the initialization of an arithmetic block except a last stage to be in an ended or started state at the point of time when calculation is ended.
SOLUTION: A last loop detecting circuit 35 outputs a last loop detecting signal at the point of time when calculation is executed in the last loop so as to establish the output of the arithmetic block 2, a control circuit 31 changes- over a loop selector 32 into an input latch 33 side and the loop is disconnected. When calculation proceeds and the output of the arithmetic block 5 is established, an arithmetic end detecting circuit 10 outputs an arithmetic end detecting signal and the output of the arithmetic block 5 is latched by an output data latch 30. At this time, the loop selector 32 is at the input data latch 33 side and calculation is temporarily stopped here. In this state, the respective arithmetic blocks 1-4 except the last stage arithmetic block 5 are in a state where whole initialization is ended or initialization is under execution.
Inventors:
Yukio Endo
Application Number:
JP31230697A
Publication Date:
July 21, 2004
Filing Date:
November 13, 1997
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F7/00; (IPC1-7): G06F7/00
Domestic Patent References:
| JP7028642A | ||||
| JP4165421A | ||||
| JP5289869A |
Attorney, Agent or Firm:
Hidekazu Miyoshi
Yasuo Miyoshi
Iwa Saki Kokuni
Kawamata Sumio
Yasuo Miyoshi
Iwa Saki Kokuni
Kawamata Sumio