Title:
ASYNCHRONOUS COUNTER
Document Type and Number:
Japanese Patent JPH06216762
Kind Code:
A
Abstract:
PURPOSE: To enable the count-up and count-down of continuous pulse strings at high frequency by inverting the states of respective flip-flops(FF) between the respective pulse strings while using an asynchronous counter. CONSTITUTION: While the clock input of D type FF at the counter is connected to a common line I, the states of respective FF D0 , D1 ... are inverted and after the even number of respective inverted pulses I, these states are set again by a pulse S. Thus, the difference in the numbers of pulses in preceding two pulse strings is applied for each 2nd pulse 1 by an output Q* of all the FF. The set pulse S for setting an output Q to 1 and resetting the outputs Q* is supplied before 1st and 3rd pulse strings. The inverted pulse string is supplied after the respective pulse strings and before the set pulse S. In order to prevent a switch 40 from being changed over to the side of I before the lapse of time enough for changing the state Q of FF on the preceding stage, the common line SW is provided with a delay circuit Td.
Inventors:
JIYANNRUI BONO
Application Number:
JP31279593A
Publication Date:
August 05, 1994
Filing Date:
November 19, 1993
Export Citation:
Assignee:
SGS THOMSON MICROELECTRONICS
International Classes:
H03K23/00; H03K23/62; (IPC1-7): H03K23/62; H03K23/00
Attorney, Agent or Firm:
Keiichi Yamamoto
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