Title:
ASYNCHRONOUS DATA RECEIVING CIRCUIT
Document Type and Number:
Japanese Patent JP2014138297
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To obtain an asynchronous data receiving circuit for receiving data correctly even when there is a deviation between a receive clock frequency and a system clock frequency inputted together with data.SOLUTION: The asynchronous data receiving circuit comprises: a clock phase determination unit 140 for determining proximity between the phase of the receive clock and the phase of a positive-phase clock synchronized to the system clock, and determining proximity between the phase of the receive clock and the phase of an inverse-phase clock 180 degrees out of phase with the system clock; a received data inverse-phase sampling unit 162 for sampling and latching received data with the positive-phase clock; and a data selector 190 for selecting output of the received data inverse-phase sampling unit 162 when the clock phase determination unit 140 determines proximity between the phase of the receive clock and the phase of the positive-phase clock, or selects output of a received data positive-phase sampling unit 161 when proximity between the phase of the receive clock and the phase of the inverse-phase clock is determined.
Inventors:
SATO HIDENORI
Application Number:
JP2013006233A
Publication Date:
July 28, 2014
Filing Date:
January 17, 2013
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H04L7/04
Domestic Patent References:
| JP2005012305A | 2005-01-13 | |||
| JP2005339519A | 2005-12-08 | |||
| JPH10247903A | 1998-09-14 | |||
| JP2005012305A | 2005-01-13 | |||
| JP2005339519A | 2005-12-08 | |||
| JPH10247903A | 1998-09-14 |
Foreign References:
| US20030115498A1 | 2003-06-19 | |||
| US20030115498A1 | 2003-06-19 |
Attorney, Agent or Firm:
Tadahiko Inaba
Kanako Murakami
Shigeaki Matsui
Kuratani Yasutaka
Kanako Murakami
Shigeaki Matsui
Kuratani Yasutaka