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Title:
BIDIRECTIONAL BUS BUFFER
Document Type and Number:
Japanese Patent JPS59225422
Kind Code:
A
Abstract:

PURPOSE: To realize a bidirectional buffer without requiring a bus terminator by providing a logical gate having a data protecting function to a bus buffer path so as to fix a bus line to a high level or a low level while the bus line is not in use.

CONSTITUTION: An output of a logical gate 21 is connected to an input of a 3- state output buffer 22 and an output of a logical gate 23 is connected to an input of a tri-state output buffer 24. An output of the tri-state output buffer 24 and an input of the logical gate 21 are connected to a connecting terminal 25 of the bus line 1 and an output of the tri-state output buffer 22 and an input of the logical gate 23 are connected to a connecting terminal 26 of the bus line 2. Further, an output/input terminal of a positive feedback logical gate 27 is connected between input and output terminals of the logical gate 21 and output/input terminals of a positive feedback logical gate 28 are connected between input/output terminals of the logical gate 23. The bidirectional bus buffer is obtained with simple constitution like this.


Inventors:
SUZUKI HIROAKI
KURODA TADAHIRO
Application Number:
JP9914783A
Publication Date:
December 18, 1984
Filing Date:
June 03, 1983
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
H03K19/0175; G06F3/00; G06F13/38; (IPC1-7): G06F3/00
Domestic Patent References:
JPS5592057A1980-07-12
Attorney, Agent or Firm:
Takehiko Suzue