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Title:
FAULT DETECTING MECHANISM OF DATA CHANNEL APPARATUS
Document Type and Number:
Japanese Patent JPS59225420
Kind Code:
A
Abstract:

PURPOSE: To improve the reliability of a system by discriminating whether a fault occured in an input/output bus is a fault specific to the apparatus or a fault in the matter of the entire bus system depending on the state of a flip-flop of channel status.

CONSTITUTION: An input/output system number in a data transfer control is stored in a device number register 11 and various control of the data channel apparatus is controlled by a main control section 10 depending on the content of the register 11 via a selecting device 17. When contents of the registers 11, 12 are dissident, the content of the register 11 is transferred to the register 12 by an output of a comparator 13. If a fault takes place in the input/output signal bus 20 in this state, it is detected by a fault detector 14 and an FF15 is set. This causes a selection control line 21 to be set and a condition signal 19 to be produced, thereby transmitting a test command to the apparatus. If the bus system has a fault, the fault detection is informed to a central processing unit while FF15, 16 for channel status are set.


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Inventors:
MASUDA TAKESHI
Application Number:
JP9937783A
Publication Date:
December 18, 1984
Filing Date:
June 06, 1983
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F13/12; G06F3/00; G06F13/00; (IPC1-7): G06F3/00
Domestic Patent References:
JPS49104307A1974-10-02
Attorney, Agent or Firm:
Akio Takahashi