PURPOSE: To realize the simple and inexpensive binary counter.
CONSTITUTION: When the up-count mode is commanded by an up/down control signal, a binary data stored in each of flip-flops 3a-3n is converted into 1's complement and then converted into 2's complement, and the binary data after the conversion of 2's complement is used to rewrite a storage data in each of the flip-flops 3a-3n. Thus, the binary data stored in each of the flip-flops 3a-3n is incremented by one. On the other hand, when the down-count mode is commanded by the up/down control signal, the binary data stored in each of flip-flops 3a-3n is converted into 2's complement and then converted into 1's complement, and the binary data after the conversion of 1's complement is used to rewrite the storage data in each of the flip-flops 3a-3n. Thus, the binary data stored in each of the flip-flops 3a-3n is decremented by one.
JPH0695847 | PARTIAL SEQUENCE CONVERSION REGISTER |
JPS54127645 | FULL SUBTRACTOR USING JOSEPHSON LOGIC GATE |
JPH07104776 | [Title of Invention] Addition circuit |
KIMURA MASATOSHI