Title:
BINARY SIGNAL DECODER CIRCUIT
Document Type and Number:
Japanese Patent JP3860022
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a decoding technique in which an erroneous discrimination hardly occurs even when a baseband signal is distorted or a noise is contained and a waveform is distorted.
SOLUTION: A binary signal decoder circuit is provided with an inverter circuit 2 for inverting a polarity of a baseband signal S2 as a decoding target, a peak hold circuit 3 in which an inverted signal S3 is inputted for holding the positive or negative peak value of the inputted inverted signal S3 and for inverting a polarity direction holding the peak value when a signal having a prescribed difference in a polarity direction reverse to the held peak value is inputted, and a code discriminating circuit 4 for comparing the baseband signal S2 with a peak value signal S4 held by the peak hold circuit 3, discriminating the code of the baseband signal S2 and outputting a decoded signal S5.
Inventors:
Norika Sakurai
Application Number:
JP2001362735A
Publication Date:
December 20, 2006
Filing Date:
November 28, 2001
Export Citation:
Assignee:
Icom Co., Ltd.
International Classes:
H03K5/08; H04L27/14; (IPC1-7): H04L27/14; //H03K5/08
Domestic Patent References:
| JP11355360A | ||||
| JP2104020A |
Attorney, Agent or Firm:
Katsunori Sugimoto
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