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Title:
DECODING CIRCUIT AND DECODING METHOD
Document Type and Number:
Japanese Patent JP3860023
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To provide a method for decoding a cyclic code and a decoding circuit in which a coefficient calculation circuit of an error position multinomial equation Λ (Z) is the same, a repetition count of a calculation loop is always a fixed count, and a condition determination is small, in the method for decoding a cyclic code and the decoding circuit in which t-piece or less of error is correctable.
SOLUTION: With the arrangement, a calculation is made in a coefficient calculation circuit 16 of an error position multinomial equation by using a matrix-reduction algorithm in a matrix of (t+1) row and t column obtained by adding an additional row of 1 row and t column to a Hankel matrix (square matrix). Thus, the coefficient calculation circuit 16 of the error position multinomial equation is same, a repetition count of a calculation loop is always a fixed count (the error correctable number: t times), and a condition determination is small, so that an increase in a circuit size can be restricted.


Inventors:
Tatsuo Sugimura
Yu Fujita
Takaki Shibata
Application Number:
JP2001368613A
Publication Date:
December 20, 2006
Filing Date:
December 03, 2001
Export Citation:
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Assignee:
Tatsuo Sugimura
Japan Radio Co., Ltd.
International Classes:
G06F11/10; H03M13/15; (IPC1-7): H03M13/15; G06F11/10
Domestic Patent References:
JP1158826A
Other References:
藤原寛,杉村立夫,有限体系列の周波数領域における考察,電子情報通信学会技術報告(CS94-46),日本,社団法人電子情報通信学会,1994年 6月22日,Vol.94 No.107,pp.61-66
今井英樹,符号理論,日本,社団法人電子情報通信学会,1996年 5月25日,6版,pp.123-128
Attorney, Agent or Firm:
Kenji Yoshida
Jun Ishida



 
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