Title:
BIT ERROR MEASURING UNIT
Document Type and Number:
Japanese Patent JP3536071
Kind Code:
B2
Abstract:
PURPOSE: To obtain means for measuring the logical bit position of a bit caused bit error in a digital recorder, for example, efficiently and storing the measured bit position.
CONSTITUTION: The unit for measuring the bit error by comparing a bit sequence to be measured with a correct one comprises a section 3 for storing a correct bit sequence, a comparator 7 for comparing a plurality of bits in the unit of word, a memory 6 for storing the content of a word including an error, and an error position information memory 8 indicating the position of a correct bit sequence corresponding to a bit sequence including an error. Consequently, the logical positions are stored for all bits for which the error is detected. The stored values are processed to produce bit error information of desired format.
Inventors:
Ukawa, Hiroaki
Hattori, Mutsumi
Hattori, Mutsumi
Application Number:
JP24714094A
Publication Date:
June 07, 2004
Filing Date:
September 14, 1994
Export Citation:
Assignee:
HEWLETT PACKARD JAPAN LTD
International Classes:
G06F11/267; G11B20/18; H03M13/00; (IPC1-7): G11B20/18
Attorney, Agent or Firm:
加藤 公久