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Title:
BIT PATTERN DETECTING METHOD
Document Type and Number:
Japanese Patent JP2001007799
Kind Code:
A
Abstract:

To detect a bit pattern at high speed, without lowering processing efficiency when the number of a delimiter constant (n) is made large by executing a cardinal number conversion into a 2n-ary number in order from the lower bit of a bit string for every n-bits.

A constant (n) for delimiting a bit string for every n-bits is set. Initialization is executed by setting the variable (i) of 2n-ary number to be i=0 and binary digit position variable (j) to be j=1. When the AND of the bit string and '1' is '1', the change (i=i+j) of the variable (i) is executed, and a system is moved to a carry processing. The change (j=j×2) of the digit position of a variable (j) is executed and 2n based on an n-value, which is initialized, is compared with the numeric value of (j) as the maximum digit. When they are matched, the value of the variable (i) is recorded, and presetting of the variable i=0 and position variable j=1 is conducted. The bit string is shifted to right by one bit (B=B÷2). When a termination condition is satisfied, the appearing statistics of the value of recorded 0 to 2n-1 is outputted.


Inventors:
TANIGUCHI HIROKI
Application Number:
JP17617599A
Publication Date:
January 12, 2001
Filing Date:
June 23, 1999
Export Citation:
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Assignee:
TOYO COMMUNICATION EQUIP
International Classes:
G06F7/00; H03K5/19; H04L9/22; (IPC1-7): H04L9/22; G06F7/00