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Title:
BREAK SIGNAL DETECTION SYSTEM
Document Type and Number:
Japanese Patent JPS5583927
Kind Code:
A
Abstract:

PURPOSE: To enable detection of the break signal in the two-wire and semi-double circuit by producing the time frame with every fixed time under data transfer via the conversion interface and then generating the break signal during that period.

CONSTITUTION: The two-wire and semi-double circuit is formed between CPU1 and terminal unit 7 via circuit control unit 2 plus conversion interfaces 3 and 6. Then the time frame is produced with every fixed time under data transfer via interface 3 and irrespective of the control given from CPU1. And unit 7 generates the break signal showing the interruption to CPU1 in the time frame mentioned above, and CPU1 detects the break signal sent from unit 7 within the time frame.


Inventors:
HAYASHI HIROSHI
OOI KIYOSHI
Application Number:
JP15876778A
Publication Date:
June 24, 1980
Filing Date:
December 19, 1978
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L29/06; G06F13/00; H04L13/00; (IPC1-7): G06F3/04; H04L13/00