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Title:
BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JPS635553
Kind Code:
A
Abstract:

PURPOSE: To build a circuit capable of an adequate supply of currents under a heavy load with noise voltages suppressed low by a method wherein time constant circuits are provided in a buffer front stage and the time length for a buffer to be turned on is subject to the time constant when a switch control signal is changed over in its polarity for the turning-on of the buffer.

CONSTITUTION: Time constant circuits 61 and 62 are connected between an input terminal 1 and buffer 7, and the buffer 7 is turned on after the passage of time from the inversion of a switch control signal (a), with the length of the time corresponding to the time constant provided by the time constant circuits 61 and 62. This design enables a MOSFET with a great driving capability to be used as the buffer 7, which means a lowered resistance to the output of the buffer 7. This also means that there will be no increase in the output terminal voltage when the buffer 7 is turned on under a heavy load, which ensures an adequate supply of currents. Noise voltages will be kept low because of the time constant governing the time the buffer 7 requires before it is turned on when the polarity is changed over of the switch control signal (a).


Inventors:
NAGANUMA MASAYUKI
Application Number:
JP14902386A
Publication Date:
January 11, 1988
Filing Date:
June 25, 1986
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L21/8234; H01L27/088; H03K19/00; H03K19/003; H03K19/0175; H03K19/094; H03K19/0952; H03K19/17; (IPC1-7): H01L27/08
Domestic Patent References:
JPS60244118A1985-12-04
JPS60160726A1985-08-22
JPS60134524A1985-07-17
JPS58196725A1983-11-16
Attorney, Agent or Firm:
Tadahiko Ito (2 outside)



 
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