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Title:
BUFFER MEMORY SYSTEM
Document Type and Number:
Japanese Patent JPS5489531
Kind Code:
A
Abstract:

PURPOSE: To increase probability that needed information is found on a buffer memory by equipping at least two buffer memories different in method of assignment to a set.

CONSTITUTION: When needed information resides in either 1st buffer memory BM11 or 2nd buffer memory BM12, that is, when either 1st comparator circuits 31 and 32 or 2nd comparator circuits 51 and 52 detect a coincidence signal, a current flag contained in corresponding control part 24 or 44 of control table 2 or 4 is updated and access to the corresponding address of BM 11 or 12 attained. Namely, when access to BM11 is made, set address SA1 of address register 1, selective address BS1 outputted from control circuit 10, and intra-block address BA of register 1 are used to apply control signal MC1 and when access to BM12 is made, on the other hand, control signal MC2 is applied from circuit 10.


Inventors:
OONO NAOYA
Application Number:
JP15882077A
Publication Date:
July 16, 1979
Filing Date:
December 27, 1977
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F12/12; G06F12/08; (IPC1-7): G11C9/00



 
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