Title:
BURN-IN TEST CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2738517
Kind Code:
B2
Abstract:
PURPOSE: To obtain the burn-in test circuit which is suitable for high integration and can conduct an efficient burn-in test in a wafer state.
CONSTITUTION: To the word line discharge path PD of a word line driver which consists of transistors 12 and 14 and drives a word line according to a row decoding signal NWEB, a control part is connected which consists of a transistor 20 that is controlled with an enable signal PWBE activated by the burn-in test and normally grounds the transistor 14 and a transistor 18 that applies a stress voltage Vbi to the transistor 14 by trial. The control part is provided in common to many word line drivers. The word line drivers are used in common for both ordinary operation and the test, so superior integration is obtained as compared with conventional constitution wherein a transistor for stress application is provided at each word line end part. Further, stress can be applied to all the word lines at a time.
Inventors:
RI ZAIHYON
SEKI YOSHOKU
SEKI YOSHOKU
Application Number:
JP14189995A
Publication Date:
April 08, 1998
Filing Date:
June 08, 1995
Export Citation:
Assignee:
SANSEI DENSHI KK
International Classes:
G11C11/413; G11C11/401; G11C11/407; G11C29/00; G11C29/06; G11C29/50; G01R31/28; (IPC1-7): G11C29/00; G11C11/401
Domestic Patent References:
| JP63239670A | ||||
| JP1113999A | ||||
| JP27300A | ||||
| JP4311898A | ||||
| JP676599A |
Attorney, Agent or Firm:
Takeshi Takatsuki