Title:
CACHE MEMORY DEVICE
Document Type and Number:
Japanese Patent JP3176255
Kind Code:
B2
Abstract:
PURPOSE: To shorten time required for invalidation in the case of making a cache memory invalid for massive and continuous main storage areas.
CONSTITUTION: An address generating circuit 200 generates an end address from a start address to be an invalidated object, a distance between elements and the number of processing elements. According to the value of a counter 330, the contents of respective lines in address arrays 351 and 352 are successively read out and an address comparator circuit 360 judges whether these values are included in the range from the start address to the end address. Concerning the lines in the range to be invalidated, any correspondent valid memory 431 or 432 is made invalid by an invalidation control circuit 440.
Inventors:
Takahiko Uesugi
Application Number:
JP14276295A
Publication Date:
June 11, 2001
Filing Date:
June 09, 1995
Export Citation:
Assignee:
NEC
International Classes:
G06F12/08; (IPC1-7): G06F12/08
Domestic Patent References:
| JP2294866A | ||||
| JP352066A | ||||
| JP2184971A | ||||
| JP3244065A | ||||
| JP63121975A |
Attorney, Agent or Firm:
Naoki Kyomoto