CACHE MEMORY INCORPORATED MEMORY DEVICE

Title:

CACHE MEMORY INCORPORATED MEMORY DEVICE

Document Type and Number:

Japanese Patent JPH07312084

Kind Code:

A

Abstract:

PURPOSE: To realize high speed writing for a cache memory.

CONSTITUTION: A initializing circuit 21 for a pair of data line is connected to a pair of data line DL, /DL. The initializing circuit 21 makes the pair of data line DL, /DL the same potential by short-circuiting or pre-charging. The initializing circuit 21 is controlled by an initialization control circuit 24. A first transfer gate 12 or a second transfer gate 13 is opened after short circuit or pre-charge of the pair of data line DL, /DL is finished, and data is written in a cache memory 11. The first transfer gate 12 is controlled by a control circuit 22, and the second transfer gate 13 is controlled by a column decoder (control circuit) 24.

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Inventors:

SATO KATSUHIKO
MIYANO SHINJI
YABE TOMOAKI
FURUYAMA TORU

Application Number:

JP10388294A

Publication Date:

November 28, 1995

Filing Date:

May 18, 1994

Export Citation:

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Assignee:

TOSHIBA CORP

International Classes:

G11C11/409; G06F12/08; G11C7/10; G11C11/00; G11C11/401; G11C11/407; (IPC1-7): G11C11/407; G06F12/08

Attorney, Agent or Firm:

Takehiko Suzue

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