Title:
CACHE MEMORY SYSTEM
Document Type and Number:
Japanese Patent JP3139392
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a system which eliminates the reverse dependency relation of data in a cache as to the cache memory system for a parallel processing system.
SOLUTION: From a thread management part 1 which manages the execution of threads in the parallel processing system, the time order relation among the threads is sent out to consistency maintenance parts 4 (4a to 4d), which when fetching desired data to cache memories 3 (3a to 3d), take data inconsistent to a main memory 11 out preferentially when there is the inconsistent data in the cache memory 3 attached to thread execution parts 2 (2a to 2d) executing precedent threads. For data writing, when data in the same address is held in the cache memory 3 attached to a thread execution part which follows in the time order relation, the write data is reflected on the cache memory 3 attached to the following thread execution part 2 as well as the cache memory 3 attached to a thread execution part 2 having written the data.
Inventors:
Atsushi Torii
Application Number:
JP28917996A
Publication Date:
February 26, 2001
Filing Date:
October 11, 1996
Export Citation:
Assignee:
NEC
International Classes:
G06F9/38; G06F9/46; G06F9/52; G06F12/08; G06F15/16; G06F15/177; (IPC1-7): G06F12/08; G06F12/08; G06F9/46
Other References:
【文献】Manoj Franklin,”Multi-Version Caches for Multiscalar Processors”,Proceedings of 1st International Conference on High Performance Computing,1995年
Attorney, Agent or Firm:
Asamichi Kato