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Title:
CACHE PREFETCH SYSTEM
Document Type and Number:
Japanese Patent JP2003044357
Kind Code:
A
Abstract:

To realize a cache prefetch system capable of evading useless prefetch and to exert an effect even to discontinuous block access.

An address array 100 can obtain individual retrieval results by performing simultaneous retrieval by two different addresses. A comparator 30, a prefetch validity deciding device 40 and a selector 50 update prefetch information in the address array 100 on comparing an address in a cache address holding register 10 with an address in an immediately before access address holding register 20 and confirming that both are different. A prefetch execution judging deciding device 80 and a prefetch executing device 90 execute the prefetch to the cache about a block to be prefetched to a certain block on confirming that a prefetch flag to the block in the address array 100 is valid in the case of cache access for the block.


Inventors:
KAZUNO MASANORI
Application Number:
JP2001227180A
Publication Date:
February 14, 2003
Filing Date:
July 27, 2001
Export Citation:
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Assignee:
NEC COMPUTERTECHNO LTD
International Classes:
G06F12/08; G06F9/32; G06F9/34; (IPC1-7): G06F12/08
Attorney, Agent or Firm:
Kawahara Junichi