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Patent Searching and Data


Title:
CALIBRATION SYSTEM FOR VARIABLE DELAY CIRCUIT
Document Type and Number:
Japanese Patent JPH06188700
Kind Code:
A
Abstract:

PURPOSE: To realize a highly accurate semiconductor test equipment or the like by calibrating a delay time width of a variable delay circuit mounted on a timing generator and varying the delay time at a high resolution based on an oscillated period of a highly accurate frequency synthesizer.

CONSTITUTION: A period counter 2 counts clocks 101 generated from a reference clock generator 1, a period signal 102 passes through rough delay counters 10, 20 and variable delay circuits 12, 22 being calibration objects, and timing signals 112, 113 are obtained and the phases are compared by a phase comparator 5. Each delay circuit is controlled by data from the rough delay registers 11, 21 and accurate delay registers 13, 23. A controller controls the timing generator to obtain a prescribed delay resolution subject to calibration.


Inventors:
SUGA TAKU
HAYASHI YOSHIHIKO
Application Number:
JP33831292A
Publication Date:
July 08, 1994
Filing Date:
December 18, 1992
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G01R31/28; H03K5/135; (IPC1-7): H03K5/135
Attorney, Agent or Firm:
Ogawa Katsuo