Title:
CARRY SIGNAL GENERATING CIRCUIT FOR SYNCHRONOUS
Document Type and Number:
Japanese Patent JPH05308279
Kind Code:
A
Abstract:
PURPOSE: To obtain the carry signal generating circuit for a synchronous counter suitable for a high speed logic circuit system by adopting the circuit configuration in which a carry signal and a counter output are changed in a same timing.
CONSTITUTION: The circuit is provided with decode circuits (7, 8) generating a signal in one preceding state with respect to the state of a counter requiring production of a carry signal CA and a delay flip-flop D-FF4 operated synchronously with the synchronous counter, an output of the decode circuits (7, 8) is connected to an input of the delay flip-flop D-FF4 and the output of the delay flip-flop D-FF4 is clocked again by itself to obtain a carry output.
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Inventors:
SEKI SHOHEI
YAMADA HIROYUKI
YAMADA HIROYUKI
Application Number:
JP11029092A
Publication Date:
November 19, 1993
Filing Date:
April 28, 1992
Export Citation:
Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H03K23/00; (IPC1-7): H03K23/00
Attorney, Agent or Firm:
Mamoru Shimizu (3 outside)