PURPOSE: To provide frequency division output with duty 1/2 by inputting the output waveform of an MSD-FF synchronizing with a positive phase clock and a D-latch output waveform synchronizing with a negative phase clock, and setting the output as final frequency division output.

CONSTITUTION: Forward output Q(n+1)/2 at a final stage MSD-FF.D(n+1)2 goes to 1 and simultaneously, the final output also goes to 1 via an OR gate OR at the leading edge of an (n+1)/2-th positive phase clock C. QL goes to 1 at a time 1/2 of an (n+1)/2-th clock cycle. The Q(n+1)/2 goes to 0 at the leading edge of an n-th positive phase clock C, and such information is shifted backward to a 1/2 period, and the QL goes to 0 at the leading edge of an n-th negative phase clock CB. Another input remains at 0 at this time, and the final output B also goes to 0 at the leading edge of the n-th negative phase clock CB. Therefore, a period where the state 1 of the output B can be held is between the leading edge of the (n+1)/2-th positive phase clock C and that of the n-th negative phase clock, thereby, an n-frequency division signal with duty 1/2 can be obtained.