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Patent Searching and Data


Title:
CIRCUIT DIVIDING SYSTEM FOR PARALLEL CIRCUIT SIMULATION
Document Type and Number:
Japanese Patent JPH06195410
Kind Code:
A
Abstract:

PURPOSE: To reduce a processing time by saving the number of nodes of a circuit by executing a hierarchizing processing while executing circuit division.

CONSTITUTION: In an update processing 3, the largest slave circuit among existing slave circuits is chosen to be a division object, the slave circuit chosen by the update processing 3 is divided into two to be new slave circuits. Besides, in a hierarchizing processing 5, when the number of the slave circuits to which the master circuit referring to the new slave circuits is larger then a fixed number because of making the new slave circuits, an intermediate master circuit referring to only the two newly-prepared slave circuits is prepared so as to hierarchize the intermediate master circuit to be refered to by a conventional master circuit. Then, in a judgement processing 6, when the number of the slave circuits is equal to the number of processors, the slave circuits are respectively set to be partial circuits which are referred to by the master circuits over it or the intermediate master circuit. Thus, result output 7 is executed in a form where the inside of the master circuit refers to circuits not more than a fixed number.


Inventors:
ONOZUKA HIROMI
Application Number:
JP34459692A
Publication Date:
July 15, 1994
Filing Date:
December 24, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/25; G06F11/26; G06F15/16; G06F17/50; (IPC1-7): G06F15/60; G06F11/26; G06F15/16
Attorney, Agent or Firm:
Yosuke Goto (2 outside)