Title:
CIRCUIT FOR INTEGER MULTIPLICATION AND METHOD THEREOF
Document Type and Number:
Japanese Patent JP3129524
Kind Code:
B2
Abstract:
PURPOSE: To perform efficient arithmetic while considering carry by using a multiplier with the small number of digits for the large number of digits.
CONSTITUTION: This circuit is provided with the multipliers of m×m bits parallelly connected to an integer A of n×m bits which is inputted from a low-order digit while being divided into (n) clocks for every (m) bits and multiplies the prescribed (m) bits of an integer B of h×m bits to the respective (m) bits of the integer A, full adders of 2m bits one-dimensionally arranged corresponding to the multipliers so as to add the outputs of the multipliers, the output of the full adders at the preceding high-order digit in the case of the last clock and the carries from own full adders the time before the last time to the low-order digit, buffers to hold the carries from the full adders and to feed them back to the full adders two clocks later, and register connected between two 2m bit full adders so as to simultaneously input/output the outputs of 2m bits from the 2m bit full adders. Then, a multiplied result A.B is outputted from the low-order digit from the least-significant 2m bit full adder synchronously with the clock.
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Inventors:
Keiichi Iwamura
Application Number:
JP16707892A
Publication Date:
January 31, 2001
Filing Date:
June 25, 1992
Export Citation:
Assignee:
Canon Inc
International Classes:
G06F7/50; G06F7/52; G06F7/523; G06F7/527; G06F7/53; (IPC1-7): G06F7/52
Domestic Patent References:
| JP421026A | ||||
| JP477819A | ||||
| JP6386027A |
Attorney, Agent or Firm:
Yasunori Otsuka (1 person outside)