Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
CIRCUIT FOR PREVENTING BREAKDOWN OF INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5984454
Kind Code:
A
Abstract:

PURPOSE: To avoid the breakdown of an IC at the time of abnormal bias when a power source is OFF, etc. even if the capacitance of a ripple removing capacitor in a power source circuit is reduced by mounting a diode outside between an external terminal and an external power source terminal.

CONSTITUTION: The mount-out diode D1 whose anode is connected to the external terminal 9 of the IC3 and cathode to the external power source terminal 10 is connected. Thereby, even if such a discharge time of the terminal 9 and that of the terminal 10 that the potential of the terminal 9 becomes higher than that of the terminal 10 are set at the time of the OFF-state of the power source, a current flows from the terminal 9 to the terminal 10 through the diode D1, and thus the mask breakdown of the IC3 can be prevented. Thereby, it becomes unnecessary to increase the capacitance of the electrolytic capacitor C4 in the power source circuit, in order to set long the discharge time of the potential of the terminal 10; therefore the cost becomes low.


Inventors:
NODA KOUJI
Application Number:
JP19486982A
Publication Date:
May 16, 1984
Filing Date:
November 06, 1982
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
TOSHIBA KK
International Classes:
H01L27/04; H01L21/822; H01L23/58; H02H9/04; (IPC1-7): H01L23/56; H01L27/04
Attorney, Agent or Firm:
Saichi Suyama