Title:
SAMPLE/HOLD CIRCUIT
Document Type and Number:
Japanese Patent JP3869541
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a sample-and-hold(S/H) circuit, with which input/output characteristics are made satisfactory by eliminating the phase error of switching timing at the time of S/H, based on an output voltage.
SOLUTION: This S/H circuit is constituted of a switching circuit 2 of diode bridge connection, first and second pulse control current sources 11 and 12 connected to the first and second control input terminals of the switching circuit, first and second reference voltage sources 4 and 6 respectively connecting reference current sources to the first and second control input terminals, a first transistor connecting its emitter via a level shift circuit 7 to the first control input terminal, connecting its collector to the first reference voltage source and connecting its base to an output terminal 10, a second transistor connecting its emitter through a level shift circuit 8 to the second control input terminal, connecting its collector to the second reference voltage source and connecting its base to the output terminal, a holding capacitor C1 connected between the output terminal of the switching circuit and the output terminal, and high-input impedance buffer amplifier 9.
Inventors:
Makoto Ono
Application Number:
JP33478297A
Publication Date:
January 17, 2007
Filing Date:
November 20, 1997
Export Citation:
Assignee:
Olympus Endo Technology America Inc.
International Classes:
H03M1/12; G11C27/02; (IPC1-7): H03M1/12
Domestic Patent References:
| JP5067972A | ||||
| JP5114299A | ||||
| JP7176199A |
Attorney, Agent or Firm:
Kenji Mogami
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