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Patent Searching and Data


Title:
CLOCK CHANGEOVER CIRCUIT
Document Type and Number:
Japanese Patent JPH04170119
Kind Code:
A
Abstract:

PURPOSE: To attain clock changeover without causing malfunction of a logic circuit in an equipment by providing a 2nd frame pulse selection means and a latch means to the pre-stage of a system changeover frame pulse generating means.

CONSTITUTION: The circuit is provided with a 2nd frame pulse selection means 3 selecting and outputting the frame pulse of a current system among frame pulses outputted from 1st and 2nd clock sources 1, 2 by an external system changeover command signal, and a latch means 4 latching the external system changeover command signal from the output of the 2nd frame pulse selection means 2 and outputting a system selection signal. The 2nd frame pulse selection means 3 and the latch means 4 latch the system selection command signal inputted from a frame pulse generating means 22 used at the time of changing over the system till the fall of a frame pulse signal from a clock source made to the active system newly after system changeover. Thus, malfunction of a logic circuit in an equipment at system changeover is prevented.


Inventors:
KOSUDA SHINICHI
Application Number:
JP27598390A
Publication Date:
June 17, 1992
Filing Date:
October 15, 1990
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H04L1/22; H04J3/00; H04L7/00; (IPC1-7): H04J3/00; H04L1/22; H04L7/00
Attorney, Agent or Firm:
Soga Doteru (6 people outside)